Flash memory chips are predicted to begin slowing down their bit density growth in the next few years due to lithography related constraints. Nanochip is one of the startup companies which is working to get around these limitations. The company is developing a new class of ultra-high-capacity storage chips based on MEMS technology. Nanochip’s technology will enable the storage of tens of gigabytes of data per chip, the equivalent of many high-definition feature-length videos, at a substantially lower cost than today’s flash memory solutions.
The company reported last week that it raised a $14 million financing round led by Intel Capital. This new financing round will allow the company to complete development of its first prototypes later this year to support design verification testing and limited customer sampling in 2009. We spoke with Nanochip’s CEO Dr. Gordon Knight.
MEMS Investor Journal: Can you briefly talk about Nanochip and its history?
Gordon Knight: Nanochip was founded in 1996 and was a very small company until 2003. Nanochip has 8 granted U.S. patents and 34 more patent applications. Today, about 50 people worldwide are working together to bring our MEMS storage chips into production in 2010. The underlying base technology for Nanochip does not depend upon advanced lithography now or any time in the future. We can use fully discounted fabs to make our parts. Nanochip is a fabless semiconductor company and will use third-party manufacturing sources for our chips.
MEMS Investor Journal: What are objectives and milestones do you plan to accomplish with funds from the current financing round?
Gordon Knight: Complete a major portion of our first product development this year so that we can start pilot production, DVT and some customer sampling in 2009.
MEMS Investor Journal: What technology transfer and commercialization challenges are you currently encountering?
Gordon Knight: We must use an 8” MEMS fab for our manufacturing since our die size is rather large (~150 sq. mm). Manufacturing such large MEMS chips is rather new (only TI does this now with their DLP chips). So we must scale all of our outside fab partners to 8” wafers in 2008.
MEMS Investor Journal: What are the main problems with current memory and data storage technologies? Why is your technology superior?
Gordon Knight: NAND flash will start slowing down their bit density growth around 2011 when they try to go below the 32-36 nm lithography node (bit retention gets worse with bit cell reduction and SNR gets worse also – very few electrons per bit). Nanochip technology does not depend upon lithography – we write, read, and erase 15 nm bit cells today and will get to greater than 1TB per die in the future. Our technology path is just beginning.
MEMS Investor Journal: What other interesting memory technologies are currently being introduced? How do you compare with these competitors?
Gordon Knight: We know of no other memory technology in development that is not dependent upon very expensive advanced lithography.
MEMS Investor Journal: What about other start up companies such as Cavendish Kinetics? How is their approach different from yours?
Gordon Knight: Cavendish Kinetics bit cell structures are still defined by lithography. Their cell structure is much, much larger than the domains we write/read/erase today and in the future. As I said earlier, we are not aware of any semiconductor memory technology that is not dependent upon lithography and this includes Nantero, Zettacore, Cavendish Kinetics, etc. The only way they can go beyond lithography constraints is to start building their storage chips with many vertically stacked memory layers, such as Matrix Semiconductor is trying to do (SanDisk bought them a couple of years ago but their technology is write-once). And every layer adds more masks and cost to the chip.
MEMS Investor Journal: Since your technology does not depend on advanced lithography, how are you forming 15nm bit cells?
Gordon Knight: We write and read every domain with our atomic force probe tips onto a continuous media layer. There is no patterning of this layer. A good analogy is a disk drive which physically is very large, but their magnetic domains written on their disk media are extremely small, much smaller than lithography could do today. Their domains are defined by the dimensions of their head gap, our domains are defined by the electrical contact area of our tip on the media, typically in the 10 to 20 nm diameter today and going much, much smaller in the future.
MEMS Investor Journal: Where are you doing your prototyping and manufacturing?
Gordon Knight: We have four fab partners for our MEMS chips and media layers, but these partners are confidential.
MEMS Investor Journal: Who are your initial target customers? Have you shipped samples to them yet and what was their feedback?
Gordon Knight: Our first products will go into solid state disk drives, enterprise servers, laptop computers, and eventually USB drives, cell phones, etc. We do not expect to ship customer samples until sometime in 2009.
MEMS Investor Journal: What advice would you have for other companies who are commercializing MEMS technologies?
Gordon Knight: You need very strong partners who have established their ability to make MEMS devices in high volume. Our type of large MEMS device cannot be done by one company alone – we have several, very large partners in our commercialization efforts.
Dr. Gordon Knight is Nanochip’s Chief Executive Officer. Prior to joining Nanochip in 2002 Dr. Knight founded three optical storage companies: Optimem, Inc., Maxoptix Corporation, and TeraStor Corporation where he served in various capacities including Chief Technical Officer, Vice President of Engineering, and President. He also directed the optical storage research activities with Xerox Corporation at Xerox PARC during the 1970’s. Dr. Knight holds a B.S.E.E. from the Massachusetts Institute of Technology and a M.S.E.E. and Ph.D.E.E. from Stanford University.