We recently spoke with Dr. Raj Gupta, a consultant in MEMS and silicon sensors, about his experiences with fabless MEMS operations. Specifically, we discussed the transition process from prototype to volume production, the associated costs and challenges, as well as his specific experiences with some major MEMS foundries.
MEMS Investor Journal: What are the main challenges for fabless MEMS companies who are working on transitioning their products from prototypes to volume production at MEMS foundries?
Raj Gupta: There are three that readily surface: recognizing what IP to protect and how to do it, deciding a realistic estimate of the time involved in transition and qualification, and proactively working to reduce the number of customized process steps to fit into a more mainstream volume production fab. As has been common in the past, MEMS IP can be process oriented and involves trade secrets. A willingness to give up some of that may be necessary under the right business circumstances. As obvious as this may sound, the more thought that can be given upfront when developing a prototype process, the more readily it can be transitioned into high volume.
Historically, MEMS companies have been differentiated by the custom processes that they would develop for a particular product; thus, they would often build a fab around their devices. That paradigm is changing significantly as mainstream volume fabs become available, requiring either old companies to go back to the drawing boards or new companies to develop devices to an existing process, and if necessary putting MEMS processes such as bulk etching, release, and bonding into the backend where they might have more control and options.
MEMS Investor Journal: What are some typical ways to protect IP? Can you give a few specific examples?
Raj Gupta: The ideal way to protect any IP is to patent and to license it. It then becomes a negotiable entity with well-defined characteristics and bounds. Trade secrets are risky since they rarely stay that way for long and are harder to define. Stanford's patents for silicon nitride AFM cantilevers are a good example. The ones for creating oxide-sharpened cantilever tips are very application-specific and the terms of royalty are directly tied to the number of AFM cantilever tips sold to an end customer. Trade secrets which have held in piezoresistance silicon over several decades are being slowly obviated by better raw processing precision and control, and the ease and availability of integrating electronics to compensate for performance variations. Furthermore, some capabilities in CMOS, such as voltage actuation greater than 40V on the same chip with MEMS, open the door for lots of unique MEMS CMOS integrated IP.
While in the past process IP was driven by a desire to exclude competition, I feel that in the future it will be driven solely by custom and high-margin application-specific needs. CMOS-friendly MEMS for commodity applications will go the way of traditional digital electronics, where design IP is more architectural in nature and targeted towards overall system performance. The fundamentals of materials processing, such fabricating on stress-free epitaxial layers, annealing metals to reduce fatigue and extend cycling, stiction-free release and operation, and hermetic encapsulation will become the property and the responsibility of the fabs, but will be accessible to the benefit all. Most agile MEMS companies are readily taking up this shift in dynamics. The challenge is and will be for the next few years to develop qualification metrics, standards, and process test tools and test structures for monitoring the more "mechanical" aspects of materials processing - something CMOS fabs are not familiar with.
MEMS Investor Journal: How much time and money should a company budget to take a product from prototype to volume production?
Raj Gupta: The amount of time and money spent varies as dramatically as the type of devices being manufactured. Some devices can be as trivial as shallow etched features in glass; others can be multi-wafer structures that involve fusion bonding of electronics with micromechanical parts and specialized needs for dicing and hermeticity. While the former may be a 2-step mask process, the latter could be a 35-mask process. The ease of transition depends heavily on the commonality of the toolsets and the level of sophistication and experience of the engineers involved. Also, many fabs will not get involved if the process does not bring in a certain minimum amount of revenue independent of complexity involved in the process. Amounts like $1-2M per year at a mid-to-high volume fab during development phase for single-chip MEMS transducer with electronics is not unrealistic.
MEMS Investor Journal: What are the main cost components of the overall $1-2 million annual cost?
Raj Gupta: Process qualification is non-trivial. MEMS CMOS-friendly processes are not CMOS-seamless. As I alluded to earlier, fabs are not readily equipped to deal with the mechanical properties of materials, and how to test for and control them. In one very specific experience, we noted the difficultly of a fab vendor to make stress-free silicon nitride even though they had extensive experience in developing oxide-nitride dielectric anti-reflective optical coatings. The challenges for mechanical materials are unique. The early adopters and strategic partners of the high-volume fabs will bear the cost of this process evolution and technology and standards development, and this development in some notable cases has taken up to two years. The percentage of the cost dedicated to process qualification will diminish rapidly once processes become more standardized and more accessible.
MEMS Investor Journal: How would go about selecting the right foundry partners? What are the key criteria?
Raj Gupta: I look for three basic things: What is my initial and ramped up volume needs, and which fabs are best equipped to deal with that? What are my critical processing needs and fab capabilities that are essential to my product; for example: high voltage actuation, gold deposition, and wafer bonding. And lastly, what level of exclusivity can I get on custom aspects of the process or on the market that I am serving? While the former may be impossible to get, the latter is more open for negotiation. With respect to volume there is typically an inverse relationship between fab size and process customization.
MEMS Investor Journal: Which MEMS foundries have you personally worked with, for which products and what has your experience been?
Raj Gupta: I have worked and dealt with several foundries both on the East Coast such as Cronos, Rohm & Haas Electronic Materials and the West Coast such as Quicksil, Nanostructures, Crea Microsystems, IMT & Jazz as well as ST Microelectronics and NILT. The product areas have been piezoresistive wafer-bonded (anodic, thermo-compression, and glass-frit) accelerometers and pressure sensors, silicon nitride AFM cantilevers, optical switching micromirrors, and fiber-optic v-grooves.
Most of our relationships have been negotiated case-by-case. Typically the best relationships are developed when there is strategic interest of all parties involved and they tend to be long-term; this mitigates high up-front NRE costs. Often these relationships would involve both the fab and our customer with roll-out schedules and milestones that are coordinated and agreed upon among all parties. Traditional CMOS ASIC fabs are becoming more available and willing to do MEMS processing as their business is drying up to overseas markets and as MEMS products pick up volume. And, as always, it’s a good idea to use a second supplier, especially if volumes allow it.
MEMS Investor Journal: What are the main things to look out for in setting up an agreement with a foundry? What are the common areas of potential disagreements and pitfalls?
Raj Gupta: Setting realistic expectations for development efforts and for product ramp-up times and volumes. This is always hard and has always been a challenge, especially for startups; and they make up more than half of the customer base for MEMS foundries. The additional aspect is to clearly define which responsibilities of the device performance are to be handled by the fab, and which are to be handled by the designer. Standard (ideally in-situ and electronic) test structures are needed to become the deciding metric for fab performance and can serve as clear delineation of the fab’s and the designer’s responsibilities. For example, while it may be unreasonable for a fab to test for accelerometer performance such as sensitivity and drift, it may be okay for it to test for layer thicknesses, stress-gradients, sidewall profile and undercutting, all which contribute to accelerometer performance and can be correlated analytically.
MEMS Investor Journal: What do you think about TSMC's recent entry into the MEMS foundry business? How will this affect existing players?
Raj Gupta: TSMC public disclosure and open availability for doing MEMS and sensors work has long been anticipated. They have been deliberate and confidential about their activities until recently. I look forward to seeing how they will be improving and automating MEMS processes and what their plans are for back-end packaging, test, trim and calibration, and how much of that responsibility they take and how much they pass on to their customers.
I do not expect a tremendous shake-up as the markets that TSMC will serve – primarily consumer electronics is relatively new and growing. It is hard to predict how this will play out in years to come. While most of the growth has been driven by price, in the upcoming years I think we may start to see differentiation based on performance as products mature and OEM's start to get a better understanding of the needs of their product and the availability of various technologies.
MEMS Investor Journal: Do you know of any major MEMS companies who are already working with TSMC? If so, for which MEMS products?
Raj Gupta: With TSMC's recent announcement, I would venture to say that I am far behind in knowing of the latest news. I do recall that Analog Devices and MEMSIC are both strategic partners that have been involved in developing inertial sensors with them for over a year.
MEMS Investor Journal: Do you think that the recent drive by some foundries to transition to 8-inch equipment is justified? What are the key cost and benefit considerations here?
Raj Gupta: Clearly there has to be business justification for this transition. I would hope that this is based on anticipated volumes, price reductions, and larger markets. Not everything has to do with size reduction. Some sensors just do not work well when they get smaller. There may be some push derived from the sunset of legacy (small wafer size) equipment and lack of available support and infrastructure, and there may be some for marketing purposes. For boutique and low volume MEMS products this transition cannot be justified, and for an 8" fab to be able to handle custom processes, such as for AFM cantilevers, while supplying microphones on standard CMOS may not be practical. As a result, there will be further stratification of the type of fabs that are out there based on the volumes they provide, the amount of customization they can bear, and the amount of process invention that is necessary. For anyone just looking to get a MEMS chip, this is a confusing landscape.
MEMS Investor Journal: What are some of the best ways fabless companies can improve yield? Can you give a few specific examples in your experience?
Raj Gupta: This question is very specific to the processes involved. Typically, wet processes and bulk wafer etching provide the most challenges and the biggest areas of risk, and are not readily automated. The problems include: mechanical, such as the need for special jigs and fixtures; chemical, such as the need to control temperature, time and chemistry for etching selectivity and surface finish; and material protection and handling. Generally, the processes that affect yield are also throughput limiting and require manual oversight.
Raj Gupta, PhD is currently the owner of Volant Technologies (https://terahz.org), a boutique consultancy providing technical guidance in emerging technologies, specifically in silicon sensors, MEMS, MST and nanotechnology. He has been an innovator in the MEMS area for over the last fifteen years. He led IP development and strategy at Coventor and opened up its Bay Area office in 1997, helped co-found InLight Communications and secure $15M in Series-A investment, invented their free-space micromirrors technology, and developed Measurement Specialties first piezoresistive low-pressure (sub-1PSI) sensor chip. Between 2006-2007 he founded Sensamatics Corporation, and as CTO developed disruptive pressure sensing solutions for the TPMS and HVAC market. He is the author of numerous research papers and has given several invited presentations. He obtained his bachelors from the University of Illinois at Urbana/Champaign, and PhD in Electrical Engineering from MIT (Massachusetts, USA).
Copyright 2008 MEMS Investor Journal