MEMS Investor Journal: What are the typical substrate thicknesses used in TSV applications?
Chris Gudeman: There are many considerations that determine substrate thickness. For example, substrate rigidity requirements, choice of substrate material (glass vs. silicon), die size, whether or not wafer-to-wafer bonding is employed as well as robotic fab equipment requirements and limitations. Also important to consider are signal performance issues such as in RF applications because losses do scale up in RF applications for both high resistivity Si and borofloat glass substrates. Via considerations need to be taken into account -- these include fill processes limitations, diameter, depth, material, temperature budget and aspect ratio.
MEMS Investor Journal: What kinds of applications use thick substrates? What kinds of applications use thin substrates?
Chris Gudeman: Given all these considerations we see substrate thicknesses running the gamut between 20um and 500um, where RF applications are focusing on thinner substrates (<60um) and interposers on thicker substrates (> 250um).
An X-ray image of IMT’s through-silicon metal via wafers. Thermal oxide layer is used to isolate the vias from the Si substrate.
MEMS Investor Journal: Why do RF applications need thinner substrates?
Chris Gudeman: The loss tangent of high resistivity silicon is reasonably low, but it is still finite. So by making the silicon substrate thinner, the net loss is reduced. Because silicon is generally an ideal substrate, the capability to thin the silicon by back grinding -- and then the capability to handle the thin substrate -- is very important for high performance RF applications.
MEMS Investor Journal: What are interposers? What are they used for?
Chris Gudeman: Imagine a small multi-layered PCB that may have an extremely small footprint of connectivity on one side interfacing to a micro-device. The small PCB may contain complex electrical paths and circuits that re-route and/or re-characterize signals from the micro-device and in turn, interface with additional components or perhaps an entire system. Now imagine that the small multi-layered PCB is not really a PCB at all but instead, it’s a multi-wafer level packaged device with wafer levels dedicated to ground, power and signal planes. That’s an interposer. In other words, it is a PCB, but with lines and spaces that are reduced by 10x.
This image shows an example of metal traces on interposers. These traces are buried in oxide dielectric. Here, the dielectric is released to show the interconnecting matrix.
MEMS Investor Journal: Aside from silicon, what other kinds of substrates are used in through-substrate via applications?
Chris Gudeman: Demand for vias in borofloat glass has been steadily increasing. There are several companies working on vias through glass, having made progress both in hermeticity and via pitch. They are demonstrating up to 10,000 metal vias on a 6-inch glass wafer. To put this into perspective, IMT has a program where we are implementing nearly 140,000 TSVs on a 6-inch silicon wafer. It is often perceived that RF performance on borofloat glass is far superior to that on Si, however the loss tangent of borofloat is only slight lower than that of high resistivity Si. Si is really an amazing material.
MEMS Investor Journal: For each type of substrate, what are the available process choices for via etching?
Chris Gudeman: For silicon, deep reactive ion etching (Bosch process) at room temperature and, to a lesser extent, anisotropic KOH etching are available. One of our substrate suppliers uses a proprietary glass via process. IMT cannot comment on the glass via process because we do not offer this technology ourselves. At least two companies seem to offer this technology: Schott and Tecnisco.
MEMS Investor Journal: What are the costs associated with each etching process?
Chris Gudeman: It depends on how you define cost and depends on the type of via processing methods, equipment used, and labor involved. On the surface, this seems like an easy question, but there are many variables to consider. Generally, cost scales strongly with performance (resistance, bandwidth, insertion loss, etc), production volume and design specifics. Via wafer price can range between $250 and $750 per wafer in high volume. The price is dependent on many variables, such as the type of materials used, via filling (plated, sputtered, or others), the size and depth of the vias, the process used to etch the vias, substrates size (4”, 6”, 8”, and 12”), etc. At the end of the day, however, pricing is driven by market, performance, size, operating environment, materials, and other application specific requirements.
MEMS Investor Journal: Aside from costs, what are the pros and cons of each etching process?
Chris Gudeman: For the Bosch process, the benefits include high anisotropy, high rate parallel process, lithographic precision placement and high density. One problem encountered with the Bosch process is scalloped sidewalls. The main benefit of KOH process, is batch processing. The disadvantage of KOH process is the additional costs associated with creating a hardmask for this etch. The KOH etch also creates a 56.7 degree etch profile, thus taking up increased "real estate" on the wafer. Glass processes are varied and generally supplier specific.
MEMS Investor Journal: What are the main types of materials that are used to fill the vias? Briefly, how is each material used and for which applications?
Chris Gudeman: Many people are using different materials. Some of the common ones are as follows:* Cu: sputtered and electroplated, used in RF, interposer, and low impedance applications. IMT's current RF and interposer via platforms include 15 micron diameter by 50 micron depth, and 50 micron diameter by 250 micron depth.
* W: sputtered or CVD, used in RF and low impedance applications.
* Au: sputtered or electroplated, used in RF and low impedance applications
* Doped silicon: implant/doping, interposer applications
* Polysilicon: LPCVD, interposer applications
* Ag: sputtered and solder, used in similar applications as Cu vias. However, there are challenges to Ag processing, such as excessive dimples on pad surface, voids, and reactive to chemistry.
MEMS Investor Journal: What are the main challenges with via filling? What specifically causes these problems and what are some of the solutions to overcome these limitations?
Chris Gudeman: Our focus at IMT over the last 5 years has been the electroplated Cu through-wafer vias (TWVs). During this time we have solved numerous fabrication issues, including pitch-off, bubbles, porosity, plating rate, seed layer deposition, thermally induced plastic deformation, hermeticity, and methods to test and verify the yield and performance TWV. This is now an exciting technology that we bring to MEMS marketplace.
MEMS Investor Journal: What some of the most interesting applications that you’ve seen recently that utilize TSVs?
Chris Gudeman: Currently we employ the Cu via on four RF platforms, where space and insertion loss minimization are state of the art. We also use a similar technology to make a TWVs for magnetic flux! Given this technical foundation we are now developing optical and fluidic TWVs. The goal in all of these is “shorten the path”.
Copyright 2010 MEMS Investor Journal