CMP, or chemical mechanical polishing, was developed in the late 1980s at least partially as a result of a secret IBM project at the time. Although initially mainly used in CMOS processes, CMP is now increasingly being utilized by MEMS process flows. We recently spoke with Dr. Robert Rhoades, CTO of Entrepix, about the history of CMP, current trends as well as traditional and emerging CMP MEMS applications. In this comprehensive interview, Robert also provides his insights on the current CMP cost trends and the emerging 3D stacking and TSV technologies.
MEMS Investor Journal: What is CMP? Can you briefly describe the basic process and what it does?
Dr. Robert Rhoades: CMP stands for chemical mechanical polishing (or planarization in some references). The primary purpose of CMP is to differentially remove material (bulk or deposited films) from raised areas on a surface faster than adjacent low areas until the local topography or step height is polished flat. Most CMP applications are intended to achieve an ultraflat, ultrasmooth surface prior to the next process step.
The basic CMP process involves holding a wafer or substrate on a rotating carrier and pressing it against a larger polymeric polishing pad held down on a very flat spinning table (or platen) while flooding the interface with a liquid slurry mixture of chemistry and suspended sub-micron abrasive particles. The process pressures, speeds and choice of pad and slurry are highly dependent on the materials, thicknesses, and final surface properties required for a particular step in the fabrication sequence.
MEMS Investor Journal: What were the initial applications for CMP and when did those appear? What were the main driving factors for those initial CMP applications?
Dr. Robert Rhoades: In the late-1980s to mid-1990s, roughly at the transition period to 0.35 µm CMOS design rules, CMP emerged as the premier method for planarization of interlevel dielectric oxide layers, or ILD CMP. The topography resulting from lower levels of patterned films can create a very non-planar ILD surface, which creates severe difficulties for at least three subsequent process steps: photolithography, metal deposition and metal etch.
The depth of focus at photolithography sets an upper limit on the amount of surface height variation within a stepper field that can be accommodated and still maintain crisp definition of features over the underlying topography. In order to print smaller feature sizes, topography had to be reduced. A second problem caused by oxide topography was poor sidewall step coverage at the next metal deposition. At design rules greater than 0.35 µm, fabs used various process techniques to slope the sidewalls of vias and contacts sufficiently to get step coverage, but these tricks began failing as devices continued to shrink. In similar ways, metal etch was impacted by topography due to the amount of overetch required for complete removal of metal stringers at the bottom inside corners of features.
All three of these factors were becoming difficult or virtually impossible to solve with existing techniques until CMP was implemented. The first high volume CMP process steps were oxide CMP for ILD planarization and tungsten CMP for contacts and vias. Within a few years, STI CMP and Cu CMP were also in high volume. These four process steps still account for the vast majority of CMP unit operations, though many more materials have now been added for specialized layers in MEMS, mixed signal devices, and other advanced technologies.
MEMS Investor Journal: How did the CMP technology develop over time, including available materials and integration challenges?
Dr. Robert Rhoades: CMP was developed over several years in the late 1980s in secrecy (primarily by IBM which holds many of the early patents) and later spread through the industry. In the spirit of “a picture tells a thousand words,” SEM images of M1/M2 contacts made with and without CMP are shown below along with a six-level metallization scheme.
SEM photos showing (left) cross section of a sloped-wall M1/M2 via made without CMP, (middle) developmental M1/M2 via in same device using 2 levels of oxide CMP and 1 level tungsten CMP, and (right) multi-level interconnects enabled CMP (image courtesy of Freescale Semiconductor).
As IC technology continued evolving toward the 0.25 micron node, interconnect delays due to resistance-capacitance (RC) time constants were rapidly becoming the limiting factor for circuit speed rather than transistor gate delay which had been the traditional bottleneck. To continue shrinking design rules, the industry had no choice but to develop an interconnect scheme with lower RC time constants. With only 3 metals (gold, copper and silver) having lower resistivity than aluminum, choices were limited for lowering resistance.
All three metals had severe issues, but copper emerged as the most desirable option even though repeated attempts at developing a plasma-based copper etch failed. Therefore, rather than etching the conductive lines as had been done for decades with Al-based interconnects, the preferred method for patterning Cu interconnects became the dual damascene process. In this process, openings for lines and vias are etched into a dielectric layer and then coated with barrier metal and a sufficiently thick layer of Cu to completely overfill all features. The metal stack is then polished back to be coplanar with the underlying dielectric surface, which is similar to the making of tungsten vias or tungsten local interconnects.
MEMS Investor Journal: When and why did CMP technology begin to migrate to MEMS applications?
Dr. Robert Rhoades: Migration to MEMS devices began within a relatively short timeframe after widespread adoption of ILD CMP for planarization in CMOS fabs. Many of the MEMS issues are similar to the difficulties in CMOS devices (topography, depth of focus, and such), but with deposited films that are as much as 10-20 times thicker than the CMOS counterparts.
MEMS devices often have large beams or levers or gears that have to be fabricated in thick poly or other materials and later released to move in response to external forces. If severe topography during fabrication causes the resulting component to have sharp bends or an irregular shape, this often leads to structural weakness or reduced tolerances between moving parts in the finished device. CMP is able to planarize the surfaces during fabrication and greatly reduce these risks. Much of the early work on CMP for MEMS was done at Sandia National Laboratories in the mid-1990s.
MEMS Investor Journal: Which MEMS applications initially utilized CMP? What kinds of materials were used in these initial applications?
Dr. Robert Rhoades: Many of the early MEMS applications were various versions of accelerometers, torque sensors, and pressure sensors. Most of these types of designs rely on gears, beams, cantilevers, or membranes and include a mixture of moveable parts and fixed or anchored parts. The most common materials used in MEMS fabrication were (and still are) silicon wafers with polysilicon, deposited oxides, nitrides, and a few metal layers.
MEMS Investor Journal: What are the current trends that are driving CMP technology trends for MEMS applications? Which MEMS products, and their corresponding processes, use CMP?
Dr. Robert Rhoades: Several technology trends are impacting the use of CMP for MEMS. First, designs are becoming more complex with ever-tightening sensitivity constraints. This requires tighter tolerances between moving and non-moving components, which tightens the allowed topography and variation in physical dimensions. An optimized CMP process is often critical in maintaining these tolerances. Second, cross-functional integration of MEMS devices with non-MEMS electronic or other components is often highly desirable for both performance benefits and cost reduction (due to reduced packaging layers) or space savings (also driven by reduced packaging in many cases).
CMP enables several possibilities, such as burying MEMS devices below the surface of the Si then polishing flat to start a different type of device, or fabricating an entire CMOS circuit, then encasing it with thick oxide, and polishing the top surface smooth enough to begin the MEMS portion of the process flow. This approach is becoming very popular for sensor arrays with a CMOS driver circuit directly below each active element in the array.
MEMS Investor Journal: For MEMS applications, what are some of the new materials as well as emerging uses and integration trends?
Dr. Robert Rhoades: New materials for MEMS include polymers, metals, composites, piezoelectrics, and many more. The number of potential applications for MEMS devices is exploding and the number of materials being utilized is exploding right along with it. One example is the use of microfluidics and tiny reaction chambers to safely react substances that are normally too volatile or too exothermic to react safely in more macroscopic volumes. Some of these require catalytic surfaces or Pt electrodes as part of their design.
Another example involves fabricating piezoelectric elements into a small MEMS ultrasound transducer for miniature imaging applications. These devices are subjected to a high temperature anneal (greater than 600 degree C) during fabrication, which most metals cannot tolerate, so an alternate metallization scheme based on Pt CMP has been developed.
MEMS Investor Journal: What are the typical costs for CMP process steps and how do they generally affect the cost of a particular MEMS process?
Dr. Robert Rhoades: Costs per unit operation at any process step are highly dependent on the wafer starts rate and the overhead cost structure of the fab. It may be more relevant to highlight cost differences between typical CMP steps in a CMOS flow versus analogous CMP steps in a MEMS flow.
MEMS polish times are typically much longer by as much as 10 times, so the direct slurry cost is proportionally higher. Likewise, pad life tends to be shorter on a per wafer basis (comparable if measured in polish minutes) so effective pad cost is also higher. For some materials, such as undoped oxides, standard grade commodity silica slurries are well suited to feature sizes and defect requirements for MEMS CMP, so cost per gallon is fairly low. In more unique applications with specialty materials, the slurry may have to be custom formulated which can add substantially to the cost.
All of these factors contribute to high variability in the cost per polish, which ranges from as little as a few dollars per polish (unburdened) to well over $100 per polish in low volume applications using a specialized slurry.
MEMS Investor Journal: MEMS production is gradually shifting to 8-inch wafer size. Are there challenges with using CMP for the largest wafer sizes? If so, what are the main challenges?
Dr. Robert Rhoades: The conversion to 8-inch wafer size for CMP is a good news and bad news situation. The good news is that most 8-inch wafers utilize a notch for alignment rather than a flat, which makes the radial distribution of forces more symmetric and helps with controlling removal uniformity. The bad news is that thicker layers and longer polish times tend to exaggerate any uniformity deviations that do exist. Using stop layers can help tremendously when the design will allow their use.
MEMS Investor Journal: What about MEMS related applications that use CMP technology such as 3D integration? What are the emerging trends there?
Dr. Robert Rhoades: The trend for 3D integration is pretty simple to summarize: up! Technical conferences for the past two years have been full of presentations highlighting 3D integration and potential benefits thereof. Unfortunately, the cost is still quite high in most of the work published thus far. Teams are working hard to define better and cheaper ways to implement 3D stacking, not only with MEMS, but with virtually any other kind of chip or micro device. Some commercial products are already on the market utilizing early 3D (4G phones, iPad, etc.) and more will be launched as the technology matures and unit costs are brought down.
MEMS Investor Journal: Similarly, what do you see as emerging trends on the TSV front?
Dr. Robert Rhoades: The trendline for TSVs is parallel to that of 3D integration since most of the 3D approaches are relying on some form of TSV to connect adjacent slices. Most TSV integrations seem to be converging on Cu as the conductor, probably due to a combination of performance, widespread availability, familiarity with Cu interconnects in the CMOS world, and leveraging of CMOS fab equipment with minimal hardware adjustments. Specialty TSV applications may use poly, tungsten, Pt, or other conductive materials, but Cu is clearly the front runner.
Robert Rhoades is the Chief Technology Officer for Entrepix, Inc. He has been a recognized industry leader in chemical mechanical polishing (CMP) for over 15 years. Dr. Rhoades earned B.S., M.S. and Ph.D. degrees in Electrical Engineering from the University of Illinois. He is a named inventor on over a dozen patents and has authored more than 75 technical publications and conference presentations.
Copyright 2011 MEMS Investor Journal, Inc.