Bonding reliability testing for wafer level packaged MEMS devices

by Michael Shillinger
Vice President of Operations, Innovative Micro Technology

Devices, especially MEMS that have moving actuators, perform best inside the cleanroom.  When taken out of the cleanroom, particles can hinder or degrade the performance, and lead to device failure.  IMT, like many others in the industry, recognized the need to package these delicate devices at wafer level to ensure and optimize the device performance and shelf life.  With the advancement of wafer bonding technologies and equipment, many MEMS devices in the market today are packaged at wafer level.  At the same time, this progression has also led to the need for development of bond quality testing, especially useful for applications and devices that operate in either pressurized or vacuum environments.  The most accurate method to determine the quality of a bond is to test for package hermeticity, which consists of fine and gross leak testing.

Leak rates greater than 1x10-5 atm-cc/sec are considered gross leaks; leak rates lower than this value are considered to be fine leaks.  In general, fine leak testing consists of a vacuum cycle to remove any trapped gasses or moisture within the packaged cavity.  The device is then soaked in a helium atmosphere under pressure to drive helium atoms into all accessible spaces in the package.   Finally a precise measurement of the helium leakage rate under vacuum is made (diagram below).

Typical test set up for fine leak testing.

Gross leak testing consists of a fluorocarbon leak test.   The device is placed in a vacuum chamber to remove any trapped gasses or moisture.  Next, the package is soaked in a fluorocarbon liquid under pressure; the pressure is then turned off and the fluorocarbon liquid is heated.  Finally, a visual observation of the package is made, looking for bubbles.  There are several procedures which can test for both gross and fine leaks in MEMS devices.  In order to choose the proper testing technique, the device function and operating environment must be taken into consideration.

Typical test set up for gross leak testing.

Historically, legacy helium leak testing used the Mil-STD-883G Method 1014.11, which covers both fine and gross leak tests.  Because this test method was developed for large metal device level packaging, the resolution limitations fall short for small enclosed volume of MEMS devices.

Therefore, new tests have been developed, and this paper will discuss them in detail:

• Membrane deflection
• Radio isotope
• Cumulative Helium Leak Detection (CHLD)
• Change in resistance measurement
• Q measurement testing
• Pressurized steam

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Membrane Deflection

Membrane deflection is accurate for finding both fine and gross leaks.  In the fabrication of the lid wafer, cavities are etched which form a very thin membrane on the top surface of the lid wafer itself.  Typically these membranes are on the order of 30 microns thick.  After the lid wafer is bonded to the device wafer, the membrane deflection is measured with an optical tester (figure below).  With vertical resolution in angstroms, a small deflection of the lid membrane indicates pressure or vacuum in the package.  The membrane in the lid is convex if package is pressurized and concave if the package is in vacuum.   This fast and automated wafer-level test is non-destructive, and currently in use at IMT for production screening.  NorCom Systems also offers optical hermeticity testers for both gross and fine leak testing, utilizing digital electronic holography interferometry.  This is essentiality an interferometer with an integrated holographic camera that enables recorded images to be superimposed on the live measurement.  When applied to hermeticity testing, any small deflection on the lid membrane will indicate interference.

A Wyko interferometer image of a deflected lid membrane that indicates hermeticity.

Radio isotope

Radio isotope or radioactive decay testing is similar to helium leak testing with higher sensitivity. Packaged chips are placed in a chamber which contains pressurized, radioactive Krypton-85, and dry nitrogen.  After a period of time, the chips are removed from the chamber and measured for Kr-85 atoms using a scintillator.  Any number of atomic particles present inside the package would emit alpha radiation, indicating that the package is not hermetic.  While this methodology will detect both fine and gross leaks, it is more costly because the test is performed at die level.  Because of the use of radioactive material that requires an Atomic Energy License, it is also not very popular.  This is the most precise test for hermeticity in most situations.

CHLD

Cumulative Helium Leak Detection (CHLD) is the only hermetic device testing method currently approved by the military, Mil-STD-750 Method 1071.  This die level test is more sensitive than traditional fine and gross leak testing  used for vacuum device packaging by four orders of magnitude.  The CHLD method can detect leaks less than 1 x 10-14 ATM-cc/sec.  Besides helium, this test can also detect krypton, fluorocarbons, and argon, utilizing an integrated mass spectrometer.  Testing can be performed by using Inficon’s Pernicka Series Systems.  This system uses a specially designed cryo-pump, which accumulates all of the helium that escapes through a leak path during the test.  The rate of increase or slope of the helium signal as a ratio to a standard is observed, which determines the leak rate.

Electrical Resistance

Another hermeticity testing technique uses the electrical resistance of the MEMS device (or a test structure, such as a thermistor, fabricated alongside; figure below), compared to a baseline resistance measurement.  This is performed by measuring the resistance-hot (R-hot) and resistance-cold (R-cold)   After completion of wafer bonding and pad reveal, an automatic probe station is used to pass current through the MEMS device or a thermistor to measure resistance.

A typical thermistor used for hermeticity measurements in MEMS applications. 

In packages with low or partial pressure, there would be less heat dissipated by convection.  In higher pressure, the amount of heat dissipated by convection would increase.  These two temperature differences would change the fundamental resistance of the device.  Screening for low resistance would indicate that high vacuum is not present.  Because this is a wafer-level electrical test that allows 100% testing of every die, wafer maps can be created to identify good and bad dies (figure below).  This simplifies sorting immensely.  The low cost and speed of this automated testing is well-suited for production.

A sample thermistance map showing good and bad devices.

Q measurements

Hermeticity can also be quantified using mechanical Q measurements of MEMS resonators.   Hermetic bonding achieves vacuum levels on the order of 1 mTorr inside a wafer level package.  At this very low pressure, the viscous drag of gas on the resonator device inside the package is essentially eliminated.  The Q is strongly dependent on the pressure; therefore, high vacuum results in higher Q.  Excitation of the resonance can be driven by external transducers or using integrated electrostatic forces.  Sensing of the resonance amplitude can also be done externally (Doppler Vibrometry) or using integrated piezo-resistive devices.  This test is ideally matched for measuring resonators, since the devices require no additional test structures or electrical I/Os.  This test is also performed at wafer level, making it production friendly.

Pressurized Steam

Lastly, pressurized steam is also used for hermeticity testing.  Packaged devices are placed in an autoclave chamber.  The chamber is then filled with high temperature pressurized steam (130 °C, 2.7 ATM, and 100% RH) for a prescribed time.  If the bonding is not hermetic, the pressurized steam will penetrate through the small crevasses in the bondlines.  Devices are, then de-lidded and optically inspected for moisture or corrosion inside the packaged device.  This testing would be performed during development and for audit testing in volume production.

Conclusions

Of course, not all devices require hermeticity to function.  For example, microfluidic devices do not need to be hermetic.  They simply need to contain the fluids.  For such applications, polymer bonds are perfectly adequate.  In such cases, none of these tests would be applicable.

Due to the incredibly small cavity size of MEMS devices, higher sensitivity tests have been developed for hermeticity testing to replace traditional Mil-Std methods.  Membrane deflection testing, r-hot vs. r-cold thermistor measurement testing and Q measurement testing can all be performed at wafer-level, where automation allows for 100% testing.  Therefore, these methods offer economical solutions.  Other methods of testing that are performed at die-level or require device destruction are also valid methods of testing.  However, the cost and the destructive nature of these tests limit the use for audit purposes only.  IMT currently uses both lid deflection and thermistor measurement screening in production testing of MEMS devices.

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Michael Shillinger has 25+ years of operations management experience, including high-volume wafer manufacturing.  Previously Mr. Shillinger was the VP of Operations at Applied Magnetics Corporation, managing multiple wafer fabs and personnel for volume production of 6 inch wafers, operating 24 hours a day, 7 days a week.   He has also held the position of VP of Process Engineering and Assembly Technology.  Michael received his Masters Degree in Mechanical Engineering from Case Western Reserve University in Cleveland Ohio.  Mr. Shillinger can be reached at mjs@imtmems.com.

Copyright 2011 MEMS Investor Journal, Inc.

Comments

[Dr. MP Divakar]

Excellent article overall! I agree Mil-STD-883G Method 1014.11 is not the one to be applied to wafer-level MEMS packaging.

Question to Mr.Shillinger are:

1. You seem to favor thermistor & Q measurement methods as cost-effective ways to test for hermiticity. For non-resonant sensing strutures in a design, one would have to build Q-measuring test structures. So thermistor measurement method is the fall-back for these devices?

2. Are there any off-settings needed for resistance vs. temperature dependency in the thermistor approach?

3. What is your experience with wafers tested for hermiticity, stored for several months & retested -any degradation in hermiticity with a given process?

Dr. MP Divakar