TSVs, or through substrate vias, have become an increasingly important building block for CMOS MEMS integration, as well as for stacking of multiple IC chips. In this interview, we spoke with Tomas Bauer, VP of Sales and Business Development at Silex Microsystems about his perspective on the latest TSV trends. In particular, Tomas discusses TSV process parameters and sizes, existing and emerging applications, integration challenges, fill material comparisons and costs. He also discusses other materials for TSV substrates such as glass and silicon-glass hybrids.
MEMS Investor Journal: What are the typical substrate thicknesses used in TSV applications?
Tomas Bauer: This needs to be distinguished by product type. On the MEMS side, TSVs are either part of the substrate on which the MEMS is built, or part of the wafer cap. Substrate TSVs can be up to 600 µm thick though our standard thickness is around 430 µm. Sometimes the substrate is thinned down after wafer bonding to 100-150 µm thickness, as the bonded wafer or cap provides mechanical rigidity to the overall structure. Typically 300 µm is the minimum required for mechanical stability of the assembly and it does not really matter if that thickness is made up of MEMS wafer or cap wafer.
For interposers, thickness ranges from 300 µm and upwards, depending on assembly type. Silex specializes in rigid interposers – in other words, the interposer has mechanical strength to carry the assembly without need for additional carrier wafers and expensive bonding and debonding steps.
MEMS Investor Journal: What are interposers? What are they used for?
Tomas Bauer: Interposers are intermediate substrates between ICs and the organic substrates used in BGA assembly. They are used to achieve various advantages such as stress relief between IC and substrate thermal coefficient mismatch, higher yield by being able to subdivide a large SoC or ASIC into multiple segments (yields decrease exponentially with increasing die size), lower cost by being able to dis-integrate different technologies (such as logic, memory, flash, power, and others), IO fanout interface between SoC/ASIC (bond pitches continuing to decrease) and organic substrate (bond pitches cannot keep pace with ICs).
For MEMS, interposers provide signal routing and interconnection between MEMS and CMOS in a single package; this is called "heterogenous packaging". This has advantages over stacked and wirebonded solutions where the MEMS and CMOS are similar sizes, and minimizing the overall package footprint is of importance.
MEMS Investor Journal: What kinds of applications use thick substrates? What kinds of applications use thin substrates?
Tomas Bauer: In MEMS, a common interposer use is for intra component signal routing – that is, taking signals through the MEMS device layers for fanout and interface to driver IC chips. Silex shipped the first such interposers in mass production in 2006. This was a rigid thick interposer, enabling an all silicon package without the need for an organic substrate, and combining several chips into one "all silicon" device directly mounted on a PCB.
2.5D interposers can be thin or thick substrates. Thin substrates make plating of the via easier (less sidewall to plate) but at the expense of a lot of extra operations such as temporary bonding, silicon thinning, debonding, etc. In this process, the final structure is mounted on an organic substrate which forms the base of the final package.
A thick substrate that does not need temp bonding or thinning and is rigid enough to provide the base package framework can be advantageous and reduce overall costs, and this technology (rigid or thick interposers) is where Silex has chosen to concentrate. Note that even in applications where the organic substrate is still needed, a rigid interposer can still reduce overall handling and processing costs. Of course, overall package height restrictions can still dictate thin substrate use.
In addition, the use of rigid silicon substrate allows for integration of passives and some active elements such as steering diodes. In other words, use of TSV for passive construction means that thicker substrates give higher component value per square millimeter.
MEMS Investor Journal: What are the disadvantages of thick interposers aside from having to plate less material on the sidewalls?
Tomas Bauer: Mainly in overall package height since thick interposer adds 200+ µm to package height dimensions. Via resistance and capacitance goes up linearly with thickness as well.
MEMS Investor Journal: Why do RF applications need thinner substrates?
Tomas Bauer: Mainly to minimize insertion loss due to via-substrate capacitive coupling, and via resistance.
MEMS Investor Journal: Aside from silicon, what other kinds of substrates are used in through-substrate via applications?
Tomas Bauer: Glass is the most common other material cited, though the industry is looking at other materials (e.g. polymers) on ongoing basis. As an insulator, glass naturally has less capacitance than silicon (a semi-metal) and so it is favored for RF type applications. Hybrid silicon-glass is also being developed.
MEMS Investor Journal: For each type of substrate, what are the available process choices for via etching?
Tomas Bauer: The process choices for each are deep reactive (DRIE), laser, or wet etch. DRIE can give the tightest geometry control and, as in MEMS, can define full wafer thickness vias. For rigid interposers that need tight via pitch, organic substrates (such as a BGA substrate used in flip chip packaging) define the limit, currently between 130 and 200 µm with 200 µm being the most common DRIE is the best choice. Where wafers can be thinned prior to via formation, both laser and wet etch can be effective, though wet etch usually cannot get close to these via pitches.
MEMS Investor Journal: What about the pitch with laser etching? Please also provide some numbers for best pitches with wet etch. If the wafer is thinned to 100 µm, you can do at least 200 µm pitch with wet etch, correct?
Tomas Bauer: You are correct, laser etching can get to 200 µm pitches as well. However, Yole market research on this topic suggests that the costs of laser (versus DRIE) are higher when you get above some number of vias, 200,000 vias per wafer for example.
Wet etch is isotropic so, yes, at thin wafers, 200 µm pitch can be achieved. We do not know the processing difficulties that have to be overcome with these thin wafers since we focus on thick substrates.
MEMS Investor Journal: What are the costs associated with each etching process?
Tomas Bauer: We can’t talk specifically about cost comparisons, as Silex only offers DRIE via formation at present. However, Yole’s analysis suggests that DRIE is the most cost effective approach at the pitch of 200,000 vias per 8-inch wafer.
MEMS Investor Journal: Aside from costs, what are the pros and cons of each etching process?
Tomas Bauer: Via pitch is the main one. Substrate damage from laser drilling will likely impact the ability to form integrated passives, though we have no data on this. Wet etch through glass has the advantage of being batch process compatible which offsets the higher cost of glass substrates, though because this is an isotropic etch, the resulting vias have a 1:1 aspect ratio and subsequently cannot deliver tight via pitch.
MEMS Investor Journal: What are the main types of materials that are used to fill vias?
Tomas Bauer: Copper and gold are the most common metals used, for their ability to be seeded and plated, and their high current capabilities. Most low frequency applications can do well with our Sil-Via® process, which in fact could be looked at as an inverse of a standard TSV process where you typically fill a hole with a conductive material.
In our process, we use a highly doped silicon substrate and isolated feedthroughs are created in this substrate by etching and filling isolating trenches around the conductive silicon feed-throughs.
Another non-metal TSV technology is using doped polysilicon. While it has higher resistance than metals, doped poly or single crystal silicon vias offer better thermal matching to the surrounding substrate and processing compatibility with post-via processes. For non-RF or high speed IO applications, power and ground bussing, and control logic applications, these are superior via technologies.
MEMS Investor Journal: Briefly, how is each material used and for which applications? What are the main challenges with via filling? What specifically causes these problems and what are some of the solutions to overcome these limitations?
Tomas Bauer: For metals, it is about effective plating of high aspect ratio vias, via reliability through thermal cycling, and cost. Damascene plating of a high aspect ratio via (greater than 3) means long plating times to completely fill a long via, which has a high impact on capacity and cost. This is one of the reasons the industry has been pushing for thin wafer interposers – it is much easier to fill a 50 µm via than a 300 µm one. To provide solutions to the temperature coefficient (TC) mismatch and cost problem of thick wafer via solutions, Silex has licensed a unique technology called XiVia® from ÅAC Microtec which creates a plated via with hollow core, to allow the via to deform and compress under TC stress from the surrounding silicon as well as saving significant plating time and therefore cost.
For polysilicon, via resistance and uniformity across multiple batches is subject to tight poly deposition process control. Our Sil-Via® process avoids this by using doped substrate starting material as the basis for the via, and then trenching *around* the via and filling it with an isolating material. This is different than the approach of most other via technologies which etch out the via and then fill with a conductor. This gives advantage in via consistency and low resistance, and the ability to form vias of arbitrary size and shape, giving interposer users unique options (such as fully isolated interposer wells formed by a linked chain of Sil-Vias) for specific packaging objectives.
This article is a part of MEMS Investor Journal's ongoing market research project in the area of 3D packaging and TSV techniques. If you would like to receive our comprehensive market research report on this topic, please contact Dr. Mike Pinelis at email@example.com for more information about rates and report contents.
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