MEMS Journal -- The Largest MEMS Publication in the World: Overview of wafer level packaging technology for MEMS applications

by Michael Shillinger
Vice President of Operations, Innovative Micro Technology

Wafer level packaging (WLP) technology offers protection of delicate MEMS structures from ambient environment, providing improved reliability, performance, and reduced cost benefits to meet real world requirements. In simple terms, WLP consists of bonding a cap or a lid wafer on top of a MEMS wafer. While aspects of WLP can be modular, some customization is necessary to meet the needs of each application, where such variables include device footprint, temperature budget, allowable materials, hermeticity, absolute pressure, and cost. WLP technology is now widely used in the MEMS industry, and has contributed to mainstream acceptance of MEMS.

As compared to WLP, traditional die level packaging consists of a package with electrical interconnects, die bonding, wire bonding the die to the package then finally bonding a lid to enclose. There are many more individual components are required and the cost can add 40% to 50% to the total cost. Going forward, WLP will be a key component to hermetic and contamination-free 3D packaging that will enable vertical integration of heterogeneous functions.

The key to WLP requires selecting the bonding technique that fits the application. Successful WLP will use one or more of the following bonding techniques: metal alloy, glass frit, anodic, fusion, thermal compression, and polymer (see comparison chart below).

Metal Alloy Bonding

Metal alloy bonding is a low temperature bond (160°C to 190°C) that is hermetic and can withstand temperatures above 500°C. The bond linewidth is significantly narrower than most other bond methodologies (< 100 µm) with a tightly controlled thickness for lid-to-device wafer spacing. This technology is ideal for MEMS devices consisting of metals and oxides with different thermal expansion coefficients. When different materials are present during bonding, the lower temperature produces less inherent stress. The bond line is electrically conductive and can be used as part of an electrical circuit, including through wafer electrical connections facilitating vertical integration. Coupled with its very narrow bondline feature, this technology makes for a leading candidate when reducing the overall package footprint. It is also compatible with multiple substrate materials such as Si, glass, quartz, GaAs, AlN, SiC, Kovar, etc.

An example where the benefits of low-temperature metal alloy bonding process were beneficial -- MEMS cross-connect switch array for telephone/DSL application.

Each MEMS cross-connect switch array consists of ~100 relays, all hermetically packaged at wafer-level, where they are protected from the environment, thereby offering improved performance and reliability.

The applications that can make use of this technology today are countless but this will be significant in enabling next-generation products. For example, IR sensors will need to be smaller, lighter and lower in cost as applications range from devices carried by our soldiers to vision enhancement in automobiles. The material used for focal plane array, vanadium oxide, is unique because of its sensitivity to heat. As these devices move from chip-scale packaging to WLP, a low temperature hermetic bond technology is absolutely necessary.

ICx Photonics' IR emitter in traditional die-level packaging with a device footprint of 20 mm by 20 mm.

ICx Photonics' wafer-level packaged IR emitter with reduced device footprint of 4 mm by 4 mm.

Glass Frit Bonding

Glass frit bonding has been in use for many years, having proven hermeticity, bond strength, and reliability through much testing. This bonding technology provides excellent hermetic sealing capabilities at low cost. High vacuum (< 1 mTorr) can be achieved by combining the glass frit bond with a getter film in the wafer-level package. The bond line is relatively large with a width of ~400 µm. Although a printed bond linewidth of 200 µm is easily achieved, the resulting width will expand ~2x when reflowing the frit to form the bond. For WLP that requires high vacuum, the bond temperature of 400°C is also compatible with thin film getter activation temperature, where wafer bonding and getter activation can occur simultaneously in vacuum in the bonding system. Glass frit bonds are extremely strong and can withstand 12,000G acceleration loads. This technology is topography tolerant and the bond line can go over active circuits.

Anodic Bonding

Equally effective in bond strength to glass frit, anodic bonding involves bonding of silicon and glass wafers. It does require very clean and smooth wafer surfaces, though the bonding allows for narrower bondline geometries (< 100 µm). Bonding occurs at lower temperature of 300°C and ~300V. Especially for biological applications, this bonding method is ideal because the glass allows clear optical viewing of the encapsulated MEMS device.

For a mass sensor application that operates in fluid, both glass frit and anodic bonding methods were incorporated in developing the WLP scheme. This device fabrication requires bonding of 3 wafers: top glass lid for optical viewing, middle MEMS sensor wafer, and bottom lid wafer with getter for vacuum packaging. The sensing element is based on the AFM cantilever idea with integrated microfluidics for flowing biological materials. The high vacuum packaging enables Q > 10,000 because of low squeeze force damping of the cantilever during measurements.

Fusion Bonding

Silicon fusion bonding was first demonstrated in 1986, and consists of bonding multiple silicon wafers at high (> 1000 °C) annealing temperature, after forming the hydrogen bridge at room temperatures. While the anneal temperature may prevent the use in certain applications, for those with high thermal budget, this method offers extremely strong and hermetic bonds. For fabricating engineered substrates, such as silicon-on-insulator or forming complex silicon structures, such as pockets and cavities, cantilevers, membranes, or comb drives, fusion bonding offers predictable and reliable results.

Thermal Compression Bonding

Gold-to-gold thermal compression bonding is similar to metal alloy bonding for the hermeticity and bond strength it offers. This bonding employs a smooth sputter deposited bond line with linewidths of 50 µm minimum, on each of the mating surfaces. Process temperatures are on the order of 300°C with bond line loading of > 5 MPa. While this bonding tolerates a fraction of a micron in surface topography, the strength of this bond is higher than metal alloy bonding. Another similarity to the metal alloy bonding is the use of the bondline as electrical circuitry.

Polymer Bonding

A low cost, low temperature (~200°C), non-hermetic bonding alternative is polymer bonding (positive and negative tone photoresist, SU-8, etc). The polymer can be lithographyically defined to form the actual bond lines. Because bond line widths and heights can vary widely to suit different applications, this bonding technique is especially useful for fabricating microfluidics devices. These bonds effectively prevent particulate contamination and can tolerate significant topography; however, the resulting package is not hermetic due to gas permeation through the polymer.

Conclusion

Even before starting a single MEMS wafer, formulating a strategy for wafer level packaging will dictate the success of the MEMS program. WLP is an integral component that offers improved performance, reliability, and cost savings. The availability of many WLP platforms offers the designers a greater breadth of options that will help meet their end goals. The flexibility of WLP technology allows integration of different electrical I/O schemes, both in-plane and out of plane circuits (BWI and through-silicon vias) and fosters the integration of heterogeneous functions that were previously not possible.

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Michael Shillinger has 25+ years of operations management experience, including high-volume wafer manufacturing. Previously Mr. Shillinger was the VP of Operations at Applied Magnetics Corporation, managing multiple wafer fabs and personnel for volume production of 6 inch wafers, operating 24 hours a day, 7 days a week. He has also held the position of VP of Process Engineering and Assembly Technology. Michael received his Masters Degree in Mechanical Engineering from Case Western Reserve University in Cleveland Ohio. Mr. Shillinger can be reached at [email protected].